1. Field of the Invention
This invention relates generally to a semiconductor device and methods of fabrication thereof, and more particularly to the improved structure and methods of fabrication of a semiconductor device including MOS FET circuits and input circuits connected thereto.
2. Description of the Prior Art
In the conventional device in which MOS FET circuits are provided, some resistor circuits are connected between the electrodes of MOS FET circuits and the bonding pads connected to outer input terminals. These resistor circuits work as protection circuits for the MOS FETs and especially prevent the gate insulator of the MOS FETs from being destroyed by any surge voltage applied to the input terminal.
The resistor circuit includes a doped polycrystalline silicon layer formed in the field insulator on a semiconductor substrate and is connected to the bonding pad and the electrodes of the MOS FETs by aluminum wiring layers formed on the field insulator. The conductivity type of the polycrystalline silicon layer is generally opposite to that of the semiconductor substrate. Semiconductor regions of the same conductivity type regions as the substrate are formed underlying the field insulator in the surface of the semiconductor substrate. These regions are channel stoppers, namely, used as protective regions so that no channels are formed in the field area of the substrate.
When a high voltage is applied to the input terminal of this conventional type semiconductor device, so many charges, electrons or holes are generated in the protective regions at the surface of the substrate that a strong transient electric field occurs between the bonding pads, aluminum wiring layers or polycrystalline resistors and the semiconductor substrate. This strong transient electric field often destroys the field insulator, especially under the bonding pads or polycrystalline resistors. As a result, the bonding pads or polycrystalline resistors are electrically connected to the substrate, and the input signal fails to be transmitted normally thereafter.
Japanese patent application No. 44-20177 discloses a semiconductor device structure including a semiconductor substrate having a first conductivity type, a second conductivity type region formed in the substrate, a gate insulating material covering the substrate and a bonding pad formed on the insulating material positioned above the second conductivity type region. This structure, however, has no protection resistor. Accordingly, this Japanese patent application has little relation to this invention.